When a plurality of vias are coupled to a wiring layer provided to a substrate, current may crowd into a particular via. Thus, a method for inhibiting current from crowding into a particular via is suggested. One example is a method that inhibits current from crowding into the vias at both ends by making the electrical resistance of the wiring layer in the regions between the vias at both ends and the vias next to the vias at both ends greater than the electrical resistance in other regions as disclosed in, for example, Japanese Patent Application Publication No. 2010-62530. In addition, a method that averages the currents flowing through a plurality of vias by configuring the central points of the vias to be included in a region within a predetermined distance from the center point of the power supply pad has been known, as disclosed in, for example, Japanese Patent Application Publication No. 2015-146382.
Furthermore, a method that reduces the variation in power-supply voltage in a circuit substrate by arranging a Large Scale Integration (LSI) having the largest power consumption near the power source and configuring a power supply pattern from the power source to the LSI to be the widest as disclosed in, for example, Japanese Patent Application Publication No. 2002-374048.